1. Field of the Invention
The invention relates in general to a non-volatile memory (NVM) device, and more particular, to a structure, a fabrication method and an operation method of a p-channel flash memory device.
2. Related Art of the Invention
Being able to repetitively perform data writing, reading and erasing operations and having the advantage that the written data does not disappear after power down, the flash memory device has become a broadly applied non-volatile memory device in personal computer and electronic equipment.
The typical flash memory device comprises a doped polysilicon floating gate and control gate. During the programming or erasing operation of the flash memory device, appropriate voltages are applied to the drain region, the source region and the control gate, respectively, such that electrons are either injected into the floating gate or pulled out from the floating gate.
Generally speaking, the commonly applied mode for electron injection in a flash memory device includes channel hot-electron injection (CHEI) and Fowler-Nordheim (F-N).tunneling. The ways for programming and erasing are varied according to the injection and pulling modes.
In addition, according to the structure, the flash memory device is divided into the p-channel flash memory device and n-channel flash memory device. Having the properties of higher electron injection efficiency, higher device scalability, immunity of reliability problem caused by hot-hole injection, and lower oxide electric field for electron injection, the p-channel flash memory device has a large potential for further development.
The p-type flash memory device normally uses channel hot-electron (CHE) injection mode to write data into the drain region for programming, and uses F-N tunneling effect to pull out electrons from the channel region for the erase operation.
As the p-channel flash memory uses channel hot-electron injection for programming, the electrons are injected from a position close to the drain region only. Consequently, the electron injection efficiency is low. Normally, a higher voltage is supplied to provide a larger current, so as to increase the programming speed. As the voltage is increased, the reliability of the electronic device is reduced, so that the device shrinkage is limited.
The present invention provides a structure, a fabrication method and an operation method of a flash memory device to prevent the tunneling oxide from experiencing a very high electric field, so that the lifetime and reliability of the tunneling oxide are improved, and the integration of the flash memory device is increased.
The structure, the fabrication method and the operation method of a flash memory device provided by the present invention further increases the programming speed of the memory cells and reduces the leakage current occurring to the reading operation of the memory cells.
The structure of the flash memory device is thus provided by the present invention. The flash memory device comprises a second conductive type well formed in a first conductive type substrate, a first conductive type well formed in the first well, a stacked-gate structure formed on the substrate, a source region and a drain region formed in the substrate at respective sides of the stacked-gate structure, a second conductive type third well extending from the drain region to a position under the stacked-gate structure and with a distance spaced with the source region, and a second conductive type pocket doped region connected to the third well and the source region under the stacked-gate structure.
An n-well is formed from the side of the drain region. The n-well extends under the stacked-gate structure. A pocket doped region is formed at the side of the source region. Two sides of the pocket doped region are respectively connected to the source region and the n-well. As the pocket doped region has the higher background doping concentration compared to the n-well, and the pocket doped region has a shallow junction, it thus has an avalanche voltage between source and pocket doped region lower than that between the n-well and the source. The voltage applied to the control gate can be lower than 10 V. With the above structure, the flash memory uses avalanche induced hot-electron injection mode for programming, and uses FN tunneling effect for erasing. In addition, by short circuiting the n-well and the drain region, it can provide potential to drain and n-well, which performs read mode operation for p-channel cell.
The present invention further provides a method of fabricating a flash memory device. A first conductive type substrate on which a second conductive type first well, a first conductive type second well, and a stacked-gate structure are sequentially formed is provided. A first patterned photoresist layer that exposes a part of the substrate predetermined for forming a drain region is formed on the substrate. A first pocket ion implantation step is performed to form the exposed part of the substrate for forming a second conductive type third well that extends towards under the stacked-gate structure and is spaced with a part of the substrate predetermined for forming a source region with a distance. The first patterned photoresist layer is removed. A second patterned photoresist layer that exposes the part of the substrate predetermined for forming the source region is formed on the substrate. A second pocket ion implantation step is performed to form a second conductive type pocket doped region in the part of the substrate predetermined for forming the source region. The second patterned photoresist layer is removed. The source region and the drain region are formed in the substrate at two respective sides of the stacked-gate structure. A spacer is formed on a sidewall of the stacked-gate structure. A third patterned photoresist layer that exposes the drain region is formed on the substrate.
The substrate of the drain region is etched until reaching a junction between the drain region and the second conductive type third well, using the third patterned photoresist layer and the tacked-gate structure with the spacer. After removing the third patterned photoresist layer, a first conductive layer is formed over the substrate. The first conductive layer fills the gap space of between the stacked-gate structures and is electrically connected to the source region and the drain region. Then, a of the third conductive layer is removed, so as to form a first contact window at the source region, and a second conductive layer on the second conductive type third well. The second conductive layer is patterned to form a second contact window. The second contact window causes a short circuit between the drain region and the conductive type third well. Then, an interlayer dielectric layer is formed over the substrate and a conductive line is formed on the interlayer dielectric layer to have electrical connection with the second contact window.
The present invention uses a patterned photoresist layer to cover the region predetermined for forming the source region first. Using a tilt-angle ion implantation process, n-type dopant is implanted into the region predetermined for forming the drain region with a tilt implantation angle between 0xc2x0 to 180xc2x0. Therefore, an n-well is formed at the drain side. A thermal process is then performed to drive in the dopants into the substrate, and then the n-well extends under that stacked-gate structure. Another patterned photoresist layer is formed to cover the region predetermined for forming the drain region. Using a tilt-angle ion implantation process with a tilt-angle of 30xc2x0, an nxe2x88x92-type dopant is implanted into the predetermined drain region to form an nxe2x88x92 pocket doped region. The nxe2x88x92 pocket doped region has two sides connected to the n-well and the subsequently formed P+ source region, respectively. Using the tilt-angle ion implantation process, the n-well and nxe2x88x92 pocket doped region can be formed at predetermined regions precisely.
The present invention further provides an operation method of a flash memory device suitable for use in a p-channel flash memory device. The p-channel flash memory device has a first n-well formed in a p-type substrate, a p-well formed in the first n-well, a stacked-gate structure formed on the substrate, a source region and a drain region formed in the substrate at two sides of the stacked-gate structure, a second n-well formed in the p-well and extending towards under the stacked gate with a distance spaced from the source region, and an nxe2x88x92 pocket doped region within the distance and having two sides connected to the second n-well and the source region, respectively. The operation method includes the following steps. The stacked-gate structure comprises a control gate and a floating gate. While programming the p-channel flash memory device, a first positive voltage is applied to the control gate and the drain region is grounded. A negative current is applied to the source region. The avalanche is thus applied to cause hot-electron injection to program the p-channel flash memory device. During the erase operation, a negative voltage is applied to the control gate, while the source region is applied with a second positive voltage, the drain region is floated. The F-N tunneling effect is applied to perform the erase operation.
As the present invention uses avalanche breakdown to induce hot-electron injection mode for programming the p-channel flash memory, the programming speed can be maintained at microseconds (lower than 5 microseconds). While programming, the hot holes elapse from the source region without injecting into the tunneling oxide layer, so that the device reliability is improved. Further, the steep junction for the drain region results in a lower channel leakage current of the p-channel flash memory device. As a result, there is no need of a drain junction capable of enduring high voltage, and the device integration is further increased.
The present invention further provides an operation method of a flash memory device to operate a memory cells array. The memory cell array comprises a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are arranged in a column/row array. The drain region of each column of the memory cells is coupled to a corresponding bit line. The source region of each row of the memory cells is coupled to a corresponding source line. The gate of each row of the memory cells is coupled to a corresponding word line. During the programming operation, a first positive voltage is applied to the word line coupled to a selected memory cell, while the bit line coupled to the selected memory cell is grounded. Further, a negative current, that is, a negative voltage is connected to a source line coupled to the selected memory cell, and at the same time, the bit line coupled to the non-selected memory cells that share a common word line is floated to prevent the common word line of the non-selected memory cells from being programmed. During the reading process, the word line coupled to the selected memory cell is grounded. A second positive voltage is applied to the bit line coupled to the selected memory cell. Meanwhile, a third positive voltage is applied to a word line coupled to a plurality of non-selected memory cells. While performing erase, a negative voltage is applied to the word line coupled to the selected memory cell, while the bit line is floating and source line coupled to a positive voltage.
In the above programming operation, the common word line for the non-selected memory cells will not be programmed. This is because the bit line coupled thereto is floated, so that breakdown will not be generated at the source region of the non-selected memory cells sharing the common word line. Even though a voltage is applied to the word line, the avalanche breakdown will not occur to cause the hot-electron injection. Consequently, the non-selected memory cells will not be programmed. In addition, the voltage of the word line coupled to other non-selected memory cells is 0V. Therefore, the hot-electron injection caused by breakdown will not occur, so that the non-selected memory cells will not be programmed.
The above program operation uses avalanche breakdown to cause hot-electron injection, so that the programming speed is maintained at microseconds (lower than 5 micro-seconds). While programming, the hot holes elapse from the source region instead of being injected into the tunneling oxide layer, so that the device reliability is enhanced. Further in the present invention, the p-channel flash memory has a steep junction at the source region without sustaining high voltage. In addition, the device integration of the present invention is also increased.